1. Field of the Invention
The present invention relates to a redundancy circuit for a semiconductor integrated circuit, and in particular to an improved redundancy circuit for a semiconductor integrated circuit which is capable of accurately recognizing the position of a repaired cell after a redundancy is performed by a DRAM.
2. Description of the Background Art
In the known art, an auxiliary cell is used to prevent the entire wafer from being not used due to an error cell which is produced in the wafer after a wafer process is performed with respect to a semiconductor device such as a DRAM. Here, the error cells produced during the wafer test operation are substituted with the auxiliary cells. The above-descried auxiliary cell is called a redundancy cell.
FIG. 1 illustrates a conventional semiconductor integrated circuit which includes a row decoder 1 and a column decoder 2 receiving an address signal Ai, respectively, a cell sub-array 3 for storing and outputting a data in accordance with one selected among a word line WLi decoded by the row decoder 1 and two bit lines BITi and BITiB decoded by the column decoder 2, a sense amplifier block 4 for amplifying the data outputted from the cell sub-array 3 and outputting the thusly amplified data through input/output buses IO and IOB, and a row redundancy cell block 5 and a column redundancy cell block 6 for substituting a predetermined number of cells including the error cells when there are error cells in the cell sub array 3 with a predetermined number of word lines WL or columns. An input/output gate is provided in the interior of the sense amplifier block 4 for controlling the input/output of the data.
FIG. 2 illustrates the detailed circuits of the cell sub array 3, the sense amplifier block 4 and the column redundancy cell block 6 of FIG. 1.
As shown therein, the cell sub array 3 and the column redundancy cell block 6 are configured in a folded bit line structure in which the bit line BITi and the bit bar line BITiB are connected with the sense amplifiers 41, 42, 43 and 4R. The sense amplifier block 4 includes a plurality of input/output gates 401, 402, 403, 40R connected with the bit line BITi and the bit bar line BITiB through the sense amplifiers 41, 42, 43 and R4 and the input/output buses IO and IOB.
The input/output gates 401, 402, 403, 40R each include first switching transistors T11, T12, T13 and T1R selected in accordance with selection signals YSELi and RYSEL from the column decoder 2 and connecting the bit line BITi and input/output bus IO, and second switching transistors T21, T22, T23 and T2R selected in accordance with the selection signals YSELi and RYSEL and connecting the bit bar line BITiB and input/output bar bus IOB.
End portions of the cells M3 and M4 of the cell sub-array 3 are connected with a bit line BITO, and the bit line BITO is connected with one end of the first switching transistor T11 of the input/output gate 401, and the other end of the first switching transistor T11 is connected with the input/output bus IO. In addition, end portions of the cells M1, M2 and M5 of the cell sub-array 3 is connected with the bit bar line BITOB, and the bit bar line BITOB is connected with one end of the second switching transistor T21 of the input/output gate 401, and the other end of the second switching transistor T21 is connected with the input/output bar bus IOB.
End portions of the cells RM3 and RM4 of the column redundancy cell block 6 is connected with the bit line RBIT, and the bit line RBIT is connected with one end of the first switching transistor T1R of the input/output gate 40R through a sense amplifier 4R, and the other end of the first switching transistor T1R is connected with the input/output bus IO. In addition, end portions of the cells RM1, RM2 and RM5 of the column redundancy cell block 6 are connected with the bit bar line RBITB, respectively, and the bit bar line RBITB is connected with one end of the second switching transistor T2R of the input/output gate 40R, and the other end of the second switching transistor T2R is connected with the input/output bar bus IOB.
During the testing of the wafer, when an error occurs in the cell sub-array 3, the fuse (not shown) connected with the error cell is cut, so that the cell is not operated. At this time, the cell block in which an error occurs is substituted with the column redundancy cell block 6. In the column decoder 2, the bit line BITi and the bit bar line BITiB connected with the error cell are substituted with the bit line RBIT and the bit bar line RBITB, and the selection signal YSELi is substituted with the selection signal RYSEL.
For example, a predetermined cell among the cells M1 through M5 connected with the first bit lines BITO and BITOB is judged to have an error, the fuse (not shown) connected with each cell is cut, and the column decoder 2 outputs a selection signal RYSEL connected with the column redundancy cell block 6 instead of outputting the first selection signal YSELO. Therefore, the cells M1 through M5 are substituted with the cells RM1 through RM5 of the redundancy cell block 6. Therefore, the data to be stored into the cells M1 through M5 of the cell sub-array 3 are stored into the cells RM1 through RM5 of the column redundancy cell block 6.
In other words, assuming that the cells M1 through M5 are normally operated, the data stored in the cells M3 and M4 are carried on the bit line BITO and are transferred to the sense amplifier 41. Therefore, the switching transistor T11 of the input/output gate 401 is turned on by the first selection signal YSELO, so that the data are outputted to the outside through the input/output bus IO. In the same manner, the data stored in the cells M1, M2 and M5 are outputted to the outside through the bit bar line BITOB, the second switching transistor T21 and the input/output bar bus IOB.
On the contrary, assuming that the cells M1 through M5 are substituted with the cells RM1 through RM5 of the column redundancy cell block 6, the data stored in the cells RM3 and RM4 are carried on the bit line RBIT and transferred to the sense amplifier 4R, so that the first switching transistor T1R of the input/output gate 40R is turned on, and the data are outputted to the outside through the input/output bus IO. In the same manner, the data stored in the cells RM1, RM2 and RM5 are outputted to the outside through the bit bar line RBITB, the second switching transistor T2R and the input/output bar bus IOB.
Therefore, the data to be written into the cells M1 through M5 are written into the cells MR1 through MR5, and the selection signal YSELO from the column decoder 6 is substituted with the selection signal RYSEL.
When the repairing is finished, the cells RM1 through RM5 of the column redundancy cell block 6 operate on behalf of the cells M1 through M5 of the cell sub-array 3 containing an error, so that the circuit is normally operated.
The above-described repairing operation is performed during the testing of the wafer. Namely, the fabricator does not recognize the fact that the error cell is substituted and then the redundancy cell is used.
FIG. 3 illustrates the construction of an apparatus for checking whether the redundancy cell is used or not in the circuit of FIG. 2. As shown therein, the apparatus includes a test mode setting unit 31 for outputting a test signal TMODE in accordance with the logic states of a RAS bar signal /RAS, a CAS bar signal /CAS, a word enable signal NVE and an address signal Ai-Ak, an NMOS transistor M1 for receiving the test signal TMODE through the gate, a current limit resistor R connected between the pad 32 and one terminal 33 of the NMOS transistor M1, and a fuse F connected between the other terminal 34 of the NMOS transistor M1 and a ground terminal 35. The current limit resistor R, the NMOS transistor M1 and the fuse F are connected in series between the pad 32 and the ground terminal 35.
The operation of the circuit of FIG. 3 will now be explained with reference to FIG. 4.
The RAS bar signal /RAS, the CAS bar signal /CAS, the word enable bar signal /WE and the address signal Ai-Ak are inputted into the test mode setting unit 31, and the CAS bar signal /CAS and the word enable signal /WE are transited to a low level, respectively, and the RAS bar signal /RAS is transited to a low level. The test signal TMODE from the test mode setting unit 31 is transited to an active high state by the low level RAS bar signal /RAS, and the NMOS transistor M1 is turned on by the test signal TMODE.
Since the NMOS transistor M1, the current limit resistor R and the fuse F are connected in series between the pad 32 and the ground terminal 35, when the fuse F is cut, the current flowing path is cut. Therefore, the current does not flow through the pad 32. On the contrary, when the fuse F is not cut, a current having a predetermined level flows through the pad 32. Therefore, it is possible to check whether the fuse F is cut or not by measuring the current flowing through the pad 32, and it is possible to judge whether the redundancy cell is used or not based on the measured current value.
The redundancy circuit used in the conventional semiconductor integrated circuit is capable of preventing the entire wafer from not being used due to the error cell by judging whether the redundancy circuit is repaired or not. However, in order to check whether the cell is repaired or not, the additional apparatus shown in FIG. 3 is needed. In addition, since it is impossible to recognize an accurate information with respect to the error cell, a predetermined measurement with respect to the occurrence of the error cell is not provided. Therefore, in the redundancy circuit used in the conventional semiconductor integrated circuit, it is impossible to prevent the occurrence of the error cell.